AHCI RESEARCH GROUP
Publications
Papers published in international journals,
proceedings of conferences, workshops and books.
OUR RESEARCH
Scientific Publications
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You can use the tag cloud to select only the papers dealing with specific research topics.
You can expand the Abstract, Links and BibTex record for each paper.
2023
Dipanda, Albert; Gallo, Luigi; Yetongnon, Kokou (Ed.)
2023 17th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS) Proceedings
IEEE Computer Society, 2023, ISBN: 979-8-3503-7091-1.
Abstract | Links | BibTeX | Tags: Computer graphics, Image processing
@proceedings{dipanda202317thInternational2023,
title = {2023 17th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS)},
editor = { Albert Dipanda and Luigi Gallo and Kokou Yetongnon},
url = {https://ieeexplore.ieee.org/servlet/opac?punumber=10472709},
doi = {10.1109/SITIS61268.2023},
isbn = {979-8-3503-7091-1},
year = {2023},
date = {2023-11-10},
urldate = {2024-03-21},
publisher = {IEEE Computer Society},
abstract = {We are pleased to welcome you to SITIS 2023, the seventeenth edition of the IEEE International Conference on Signal-Image Technology & Internet-Based Systems. We thank the authors for their valuable contributions to the conference. SITIS 2023 aims to bring together researchers from the major communities of signal/image processing and information modeling and analysis, and to foster crossdisciplinary collaborations. The conference consists of two tracks: SIVT (Signal & Image and Vision Technology), which focuses on recent developments and evolutions in signal processing, image analysis, vision, coding & authentication, and retrieval techniques; and ISSA (Intelligent Systems Services and Applications), which covers emerging concepts, architectures, protocols, and methodologies for data management on the Web and the Internet of Things technologies that connect unlimited numbers of smart objects. In addition to these tracks, SITIS 2023 also features some workshops that address a wide range of related but more specific topics.},
keywords = {Computer graphics, Image processing},
pubstate = {published},
tppubtype = {proceedings}
}
We are pleased to welcome you to SITIS 2023, the seventeenth edition of the IEEE International Conference on Signal-Image Technology & Internet-Based Systems. We thank the authors for their valuable contributions to the conference. SITIS 2023 aims to bring together researchers from the major communities of signal/image processing and information modeling and analysis, and to foster crossdisciplinary collaborations. The conference consists of two tracks: SIVT (Signal & Image and Vision Technology), which focuses on recent developments and evolutions in signal processing, image analysis, vision, coding & authentication, and retrieval techniques; and ISSA (Intelligent Systems Services and Applications), which covers emerging concepts, architectures, protocols, and methodologies for data management on the Web and the Internet of Things technologies that connect unlimited numbers of smart objects. In addition to these tracks, SITIS 2023 also features some workshops that address a wide range of related but more specific topics.
Dipanda, Albert; Gallo, Luigi; Yetongnon, Kokou (Ed.)
2023 17th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS) Book
IEEE Computer Society, 2023, ISBN: 979-8-3503-7091-1, (tex.referencetype: proceedings).
Abstract | Links | BibTeX | Tags: Computer graphics, Image processing
@book{dipanda_2023_2023,
title = {2023 17th International Conference on Signal-Image Technology & Internet-Based Systems (SITIS)},
editor = {Albert Dipanda and Luigi Gallo and Kokou Yetongnon},
url = {https://ieeexplore.ieee.org/servlet/opac?punumber=10472709},
isbn = {979-8-3503-7091-1},
year = {2023},
date = {2023-11-01},
publisher = {IEEE Computer Society},
abstract = {We are pleased to welcome you to SITIS 2023, the seventeenth edition of the IEEE International
Conference on Signal-Image Technology & Internet-Based Systems. We thank the authors for their
valuable contributions to the conference. SITIS 2023 aims to bring together researchers from the major
communities of signal/image processing and information modeling and analysis, and to foster crossdisciplinary
collaborations. The conference consists of two tracks: SIVT (Signal & Image and Vision
Technology), which focuses on recent developments and evolutions in signal processing, image
analysis, vision, coding & authentication, and retrieval techniques; and ISSA (Intelligent Systems
Services and Applications), which covers emerging concepts, architectures, protocols, and
methodologies for data management on the Web and the Internet of Things technologies that connect
unlimited numbers of smart objects. In addition to these tracks, SITIS 2023 also features some
workshops that address a wide range of related but more specific topics.},
note = {tex.referencetype: proceedings},
keywords = {Computer graphics, Image processing},
pubstate = {published},
tppubtype = {book}
}
We are pleased to welcome you to SITIS 2023, the seventeenth edition of the IEEE International
Conference on Signal-Image Technology & Internet-Based Systems. We thank the authors for their
valuable contributions to the conference. SITIS 2023 aims to bring together researchers from the major
communities of signal/image processing and information modeling and analysis, and to foster crossdisciplinary
collaborations. The conference consists of two tracks: SIVT (Signal & Image and Vision
Technology), which focuses on recent developments and evolutions in signal processing, image
analysis, vision, coding & authentication, and retrieval techniques; and ISSA (Intelligent Systems
Services and Applications), which covers emerging concepts, architectures, protocols, and
methodologies for data management on the Web and the Internet of Things technologies that connect
unlimited numbers of smart objects. In addition to these tracks, SITIS 2023 also features some
workshops that address a wide range of related but more specific topics.
Conference on Signal-Image Technology & Internet-Based Systems. We thank the authors for their
valuable contributions to the conference. SITIS 2023 aims to bring together researchers from the major
communities of signal/image processing and information modeling and analysis, and to foster crossdisciplinary
collaborations. The conference consists of two tracks: SIVT (Signal & Image and Vision
Technology), which focuses on recent developments and evolutions in signal processing, image
analysis, vision, coding & authentication, and retrieval techniques; and ISSA (Intelligent Systems
Services and Applications), which covers emerging concepts, architectures, protocols, and
methodologies for data management on the Web and the Internet of Things technologies that connect
unlimited numbers of smart objects. In addition to these tracks, SITIS 2023 also features some
workshops that address a wide range of related but more specific topics.
2013
Franchini, Silvia; Gentile, Antonio; Sorbello, Filippo; Vassallo, Giorgio; Vitabile, Salvatore
Design and Implementation of an Embedded Coprocessor with Native Support for 5D, Quadruple-Based Clifford Algebra Journal Article
In: IEEE Transactions on Computers, vol. 62, no. 12, pp. 2366–2381, 2013, ISSN: 0018-9340.
Abstract | Links | BibTeX | Tags: Application-specific processors, Clifford algebra, Computational geometry, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, inverse kinematics, Motion capture, Raytracing, robotic arm, Robotics
@article{franchiniDesignImplementationEmbedded2013,
title = {Design and Implementation of an Embedded Coprocessor with Native Support for 5D, Quadruple-Based Clifford Algebra},
author = { Silvia Franchini and Antonio Gentile and Filippo Sorbello and Giorgio Vassallo and Salvatore Vitabile},
doi = {10.1109/TC.2012.225},
issn = {0018-9340},
year = {2013},
date = {2013-01-01},
journal = {IEEE Transactions on Computers},
volume = {62},
number = {12},
pages = {2366--2381},
abstract = {Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up to 5D CA operations. CliffordALU5 exploits a novel, hardware-oriented representation of the algebra elements that allows for faster execution of Clifford operations. In this paper, a prototype implementation of a complete system-on-chip (SOC) based on CliffordALU5 is presented. This prototype integrates an embedded processing soft-core based on the PowerPC 405 and a CliffordALU5 coprocessor on a Xilinx XUPV2P Field Programmable Gate Array (FPGA) board. Test results show a 5texttimes average speedup for 4D Clifford products and a 4texttimes average speedup for 5D Clifford products against the same operations in Gaigen 2, a CA software library generator running on the general-purpose PowerPC processor. This paper also presents an execution analysis of three different applications in three diverse domains, namely, inverse kinematics of a robot, optical motion capture, and raytracing, showing an average speedup between 3texttimes and 4texttimes with respect to the baseline Gaigen 2 implementation. Finally, a multicore approach to higher dimensional CA based on CliffordALU5 is discussed. textcopyright 1968-2012 IEEE.},
keywords = {Application-specific processors, Clifford algebra, Computational geometry, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, inverse kinematics, Motion capture, Raytracing, robotic arm, Robotics},
pubstate = {published},
tppubtype = {article}
}
Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up to 5D CA operations. CliffordALU5 exploits a novel, hardware-oriented representation of the algebra elements that allows for faster execution of Clifford operations. In this paper, a prototype implementation of a complete system-on-chip (SOC) based on CliffordALU5 is presented. This prototype integrates an embedded processing soft-core based on the PowerPC 405 and a CliffordALU5 coprocessor on a Xilinx XUPV2P Field Programmable Gate Array (FPGA) board. Test results show a 5texttimes average speedup for 4D Clifford products and a 4texttimes average speedup for 5D Clifford products against the same operations in Gaigen 2, a CA software library generator running on the general-purpose PowerPC processor. This paper also presents an execution analysis of three different applications in three diverse domains, namely, inverse kinematics of a robot, optical motion capture, and raytracing, showing an average speedup between 3texttimes and 4texttimes with respect to the baseline Gaigen 2 implementation. Finally, a multicore approach to higher dimensional CA based on CliffordALU5 is discussed. textcopyright 1968-2012 IEEE.
Franchini, Silvia; Gentile, Antonio; Sorbello, Filippo; Vassallo, Giorgio; Vitabile, Salvatore
Design and implementation of an embedded coprocessor with native support for 5D, quadruple-based clifford algebra Journal Article
In: IEEE Transactions on Computers, vol. 62, no. 12, pp. 2366–2381, 2013, ISSN: 0018-9340.
Abstract | Links | BibTeX | Tags: Application-specific processors, Clifford algebra, Computational geometry, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, inverse kinematics, Motion capture, Raytracing, robotic arm, Robotics
@article{franchini_design_2013,
title = {Design and implementation of an embedded coprocessor with native support for 5D, quadruple-based clifford algebra},
author = {Silvia Franchini and Antonio Gentile and Filippo Sorbello and Giorgio Vassallo and Salvatore Vitabile},
doi = {10.1109/TC.2012.225},
issn = {0018-9340},
year = {2013},
date = {2013-01-01},
journal = {IEEE Transactions on Computers},
volume = {62},
number = {12},
pages = {2366–2381},
abstract = {Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up to 5D CA operations. CliffordALU5 exploits a novel, hardware-oriented representation of the algebra elements that allows for faster execution of Clifford operations. In this paper, a prototype implementation of a complete system-on-chip (SOC) based on CliffordALU5 is presented. This prototype integrates an embedded processing soft-core based on the PowerPC 405 and a CliffordALU5 coprocessor on a Xilinx XUPV2P Field Programmable Gate Array (FPGA) board. Test results show a 5× average speedup for 4D Clifford products and a 4× average speedup for 5D Clifford products against the same operations in Gaigen 2, a CA software library generator running on the general-purpose PowerPC processor. This paper also presents an execution analysis of three different applications in three diverse domains, namely, inverse kinematics of a robot, optical motion capture, and raytracing, showing an average speedup between 3× and 4× with respect to the baseline Gaigen 2 implementation. Finally, a multicore approach to higher dimensional CA based on CliffordALU5 is discussed. © 1968-2012 IEEE.},
keywords = {Application-specific processors, Clifford algebra, Computational geometry, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, inverse kinematics, Motion capture, Raytracing, robotic arm, Robotics},
pubstate = {published},
tppubtype = {article}
}
Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up to 5D CA operations. CliffordALU5 exploits a novel, hardware-oriented representation of the algebra elements that allows for faster execution of Clifford operations. In this paper, a prototype implementation of a complete system-on-chip (SOC) based on CliffordALU5 is presented. This prototype integrates an embedded processing soft-core based on the PowerPC 405 and a CliffordALU5 coprocessor on a Xilinx XUPV2P Field Programmable Gate Array (FPGA) board. Test results show a 5× average speedup for 4D Clifford products and a 4× average speedup for 5D Clifford products against the same operations in Gaigen 2, a CA software library generator running on the general-purpose PowerPC processor. This paper also presents an execution analysis of three different applications in three diverse domains, namely, inverse kinematics of a robot, optical motion capture, and raytracing, showing an average speedup between 3× and 4× with respect to the baseline Gaigen 2 implementation. Finally, a multicore approach to higher dimensional CA based on CliffordALU5 is discussed. © 1968-2012 IEEE.
2011
Franchini, Silvia; Gentile, Antonio; Sorbello, Filippo; Vassallo, Giorgio; Vitabile, Salvatore
A New Embedded Coprocessor for Clifford Algebra Based Software Intensive Systems Proceedings Article
In: pp. 335–342, 2011, ISBN: 978-0-7695-4373-4.
Abstract | Links | BibTeX | Tags: Clifford algebra, Computational geometry, Compute-intensive algorithms, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, Software intensive systems
@inproceedings{franchiniNewEmbeddedCoprocessor2011,
title = {A New Embedded Coprocessor for Clifford Algebra Based Software Intensive Systems},
author = { Silvia Franchini and Antonio Gentile and Filippo Sorbello and Giorgio Vassallo and Salvatore Vitabile},
doi = {10.1109/CISIS.2011.55},
isbn = {978-0-7695-4373-4},
year = {2011},
date = {2011-01-01},
pages = {335--342},
abstract = {Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the architecture of CliffoSorII (Clifford coprocessor II), an embedded coprocessor that offers direct hardware support to Clifford algebra operations, is introduced. The coprocessor has been designed, implemented and tested on a Field Programmable Gate Array (FPGA) board. The experimental results show the potential to achieve a 20x speedup for Clifford sums and differences and a 5x speedup for Clifford products against the analogous operations in Gaigen, a standard geometric algebra software library generator for general purpose processors. An execution analysis of a ray tracing application is also presented. textcopyright 2011 IEEE.},
keywords = {Clifford algebra, Computational geometry, Compute-intensive algorithms, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, Software intensive systems},
pubstate = {published},
tppubtype = {inproceedings}
}
Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the architecture of CliffoSorII (Clifford coprocessor II), an embedded coprocessor that offers direct hardware support to Clifford algebra operations, is introduced. The coprocessor has been designed, implemented and tested on a Field Programmable Gate Array (FPGA) board. The experimental results show the potential to achieve a 20x speedup for Clifford sums and differences and a 5x speedup for Clifford products against the analogous operations in Gaigen, a standard geometric algebra software library generator for general purpose processors. An execution analysis of a ray tracing application is also presented. textcopyright 2011 IEEE.
Franchini, Silvia; Gentile, Antonio; Sorbello, Filippo; Vassallo, Giorgio; Vitabile, Salvatore
A new embedded coprocessor for Clifford Algebra based software intensive systems Proceedings Article
In: pp. 335–342, 2011, ISBN: 978-0-7695-4373-4.
Abstract | Links | BibTeX | Tags: Clifford algebra, Computational geometry, Compute-intensive algorithms, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, Software intensive systems
@inproceedings{franchini_new_2011,
title = {A new embedded coprocessor for Clifford Algebra based software intensive systems},
author = {Silvia Franchini and Antonio Gentile and Filippo Sorbello and Giorgio Vassallo and Salvatore Vitabile},
doi = {10.1109/CISIS.2011.55},
isbn = {978-0-7695-4373-4},
year = {2011},
date = {2011-01-01},
pages = {335–342},
abstract = {Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the architecture of CliffoSorII (Clifford coprocessor II), an embedded coprocessor that offers direct hardware support to Clifford algebra operations, is introduced. The coprocessor has been designed, implemented and tested on a Field Programmable Gate Array (FPGA) board. The experimental results show the potential to achieve a 20x speedup for Clifford sums and differences and a 5x speedup for Clifford products against the analogous operations in Gaigen, a standard geometric algebra software library generator for general purpose processors. An execution analysis of a ray tracing application is also presented. © 2011 IEEE.},
keywords = {Clifford algebra, Computational geometry, Compute-intensive algorithms, Computer graphics, Embedded coprocessors, Field Programmable Gate Arrays, FPGA prototyping, Geometric algebra, Software intensive systems},
pubstate = {published},
tppubtype = {inproceedings}
}
Computer graphics applications require efficient tools to model geometric objects and their transformations. Clifford algebra (also known as geometric algebra) is receiving a growing attention in many research fields, such as computer graphics, machine vision and robotics, as a new, interesting computational paradigm that offers a natural and intuitive way to perform geometric calculations. At the same time, compute-intensive graphics algorithms require the execution of million Clifford operations. Clifford algebra based software intensive systems need therefore the support of specialized hardware architectures capable of accelerating Clifford operations execution. In this paper the architecture of CliffoSorII (Clifford coprocessor II), an embedded coprocessor that offers direct hardware support to Clifford algebra operations, is introduced. The coprocessor has been designed, implemented and tested on a Field Programmable Gate Array (FPGA) board. The experimental results show the potential to achieve a 20x speedup for Clifford sums and differences and a 5x speedup for Clifford products against the analogous operations in Gaigen, a standard geometric algebra software library generator for general purpose processors. An execution analysis of a ray tracing application is also presented. © 2011 IEEE.